The present invention generally relates to a frame buffer memory for storing video data to be outputted to an image or picture display device such as a cathode ray tube (CRT) display or the like. More particularly, the invention is concerned with a frame buffer memory for display which has a storage capacity capable of storing more than two frames of video data for high definition picture consisting of pixels (picture elements) in a number unequal to 2.sup.i (where i is a given positive integer) and which permits the stored video data for a given one of the plural pictures to be displayed at a high speed.
Up to now, the terminal apparatus of a computer, a work station or the like system has been equipped with a frame buffer memory as a display dedicated memory for storing and outputting the video data to be displayed. With the phrase "frame buffer memory" or "display dedicated memory", it is intended to mean such a memory which is used for storing the video data resulting from the processing performed by a CPU (central processing unit) or other processor or the video data read out from an auxiliary storage medium such as, for example, a magnetic disc system, wherein the stored video data are read out in accordance with a predetermined sequence to be outputted or displayed on a screen of a picture display apparatus such as, for example, a CRT display. In the frame buffer memory of this type, it is commonly practiced to define two-dimensionally an address space by the addresses in the rowwise direction (hereinafter referred to as the row addresses) and the addresses in the column-wise direction (hereinafter referred to as the column addresses) for the purpose of establishing correspondence between the video data stored in the memory and the picture or image to be displayed.
A structure of a typical one of the frame buffer memories known heretofore is shown in the form of a memory map in FIG. 9 of the accompanying drawings
Referring to FIG. 9, a shape of a picture to be displayed is schematically shown at A and designated by a reference numeral 11. This display image or picture has an amount of information which is equal to x pixels (i.e. picture elements) in the horizontal (rowwise) direction and y pixels in the vertical (columnwise) direction. In this conjunction, it is assumed that the picture 11 is divided into two regions 12 and 13 in the horizontal direction, as indicated by a phantom line. A reference numeral 14 denotes the video data of one horizontal line of the picture 11. Illustrated in FIG. 9 at B is a most simplified method of address allocation or assignment to the frame buffer memory 15 for the picture 11 shown at A. Referring to FIG. 9B, a display region (space) 16 is established within the address space of the frame buffer memory 15 in which the column addresses correspond to the pixel positions in the horizontal directions with the row addresses corresponding to the pixel positions in the vertical direction. The number of the addresses in the horizontal direction of the frame buffer memory is represented by 2.sup.m and that of the addresses in the vertical direction is represented by 2.sup.n.
In the conventional semiconductor memory device, the address is expressed by a binary number. Accordingly, it is convenient from the viewpoint of hardware design that the number of the addresses in the directions rowwise and columnwise, respectively, is so determined as to equal to the i-th power of "2" where i is a given integer. However, the number of the pixels stored in the frame buffer memory for display can not always be expressed by the i-th power of "2" (i=2 given integer). By way of example, when the number of the pixels in the vertical direction exceeds 2.sup.n-1 only a small value, as illustrated in FIG. 9 at B, the number of the addresses in the rowwise direction (i.e. the number of the row addresses) has to be set at 2.sup.n. As a result, there take place many regions or areas which do not partake in the display. At present, efforts are being made to reduce more and more the manufacturing costs of the semiconductor memory. However, a high definition picture display apparatus requires the frame buffer memory having a storage capacity ranging from several mega-bytes to several ten megabytes. Consequently, occurrence of many areas playing no role in the display as mentioned above is undesirable from the stand point of economy.
Further, in some of applications of the frame buffer memory such as the image processing and the like, it is required that two or more images or pictures for display can be changed over at a high speed for the purpose of enabling image comparison before and after the processing or the edition of the images. When a number of the frame buffer memories each of the structure shown in FIG. 9B are Provided to this end, the number of the areas irrelevant to the display is correspondingly increased.
A technique for solving the problem mentioned above has already been proposed, as disclosed in, for example, Japanese Patent laid-Open No. 141485/1986 (JP-A-No. 61-141485). This prior art method is illustrated in FIG. 9 at C and D. Referring to FIG. 9C and assuming that the number of the column addresses in the horizontal direction is given by 2.sup.k, the video data of the picture or image 11 is divided into two regions (corresponding, respectively, to the regions 12 and 13 shown at A in FIG. 9) to be stored in a frame buffer memory 17 at regions or spaces 18 and 19, respectively. Parenthetically, it is assumed that the number of the row addresses in the vertical direction is given by 2.sup.j. In the example illustrated in FIG. 9D, the row addresses (2.sup.j) of a frame buffer memory 20 do not correspond to the pixel positions (y) in the vertical direction but all the pixel data are regarded as one-dimensional video data and stored at the successive addresses. By way of example, the video data of one line (corresponding to the video data 14 of one line shown at A in FIG. 9) is stored in the frame buffer memory 20 over two rows as indicated at 21 and 22.
According to the prior art method mentioned above, the semiconductor memory is assumed to be constituted by a general purpose dynamic RAM (random access memory). In recent years, however, it is common to realize the semiconductor memory for display by using a multi-port video RAM which is provided with a random port and a serial port. More specifically, the multi-port video RAM is equipped with a serial port which allows a high-speed read-out of the video data in addition to the random port of the ordinary RAM. By dedicating the serial port only to the read-out of the video data, efficiency in the access to the frame buffer memory by a CPU or a drawing processor by way of the random port can be enhanced.
Under the circumstances, application of the multi-port video RAM to the prior art frame buffer memory has been examined, which gives birth to the problems mentioned below.
The reading of the video data from the multiport RAM through the serial port is effected in such a manner that the addresses from which the video data are to be read out are set at the random port, whereon the video data of one row is transferred to a shift register provided on the side of the serial port, which is then followed by the read-out of the video data in the order of the column addresses. Accordingly, when the frame buffer memory is used in a manner illustrated in FIG. 9C, there arises such a situation in which the reading of the video data starts from an intermediate one of the column addresses in the region 19 corresponding to the region 13, because the number of the column addresses of the frame buffer memory 17 is greater than the horizontal width of the region 13 of the image or picture 11. In that case, the intermediate address differs from one to another row, which in turn means that the memory control for storing the video data in the region 19 is necessarily much complicated. Besides, in case the video data of the region 13 of the picture 11 is to be stored row by row in the region 19 of the frame buffer memory 17, the row in the number of y are required. This means that the number of rows given by 2.sup.j of the whole display region is insufficient. Consequently, the aimed effect of reducing the storage capacity can not be attained.
In conjunction with the multi-port RAM, it is further noted that the video data transfer from the random port to the serial port has to be performed in timing with the read-out of the video data from the serial port. Besides, refresh operation must be performed as in the case of the general purpose dynamic RAM, during which the ordinary write/read operation of the video data by way of the random port can not be carried out. Conventionally, the refresh operation is performed under the control of a CRT controller connected to the frame buffer memory, wherein the timing for the refresh operation is so determined as to fall within the horizontal blanking period of the video signal. Accordingly, when the frame buffer memory is configured as shown in FIG. 9 at D, the data transfer to the serial Port takes place in the course of lapse of the horizontal blanking period. As a result, the access through the random port is often interrupted.
Further, in conjunction with the prior art method illustrated at D in FIG. 9, it must be pointed out that the procedure for calculating the values of the addresses at which the video data of concern are stored is much complicated (involving correspondingly an increase in the processing time), giving rise to a problem.